1. Field of the Invention
The present invention relates to a circuit for processing a video intermediate frequency signal, and more particularly, it relates to a video detection circuit for demodulating a video signal from a video intermediate frequency signal.
2. Description of the Prior Art
FIG. 1 is a block diagram showing circuit structure of a conventional intercarrier system television receiver. A broadcasting signal received by an antenna 11 is converted by a tuner 13 to a video intermediate frequency (hereinafter referred to as VIF) signal having a video carrier frequency f.sub.p (58.75 MHz in Japan). The VIF signal includes a sound intermediate frequency signal having a sound carrier frequency f.sub.s1 (54.25 MHz in Japan). This VIF signal is amplified by an intermediate frequency amplifier 15, and supplied to a video detection circuit 17. The video detection circuit 17 detects the VIF signal, and outputs a video detection output signal. This video detection output signal includes a sound intermediate frequency signal component having a sound carrier frequency f.sub.s2 (4.5 MHz in Japan) in addition to a demodulated video signal component. The sound intermediate frequency signal is eliminated by a sound trap circuit 19, so that only the demodulated video signal is processed in a video circuit 21 and supplied to a picture tube 23. On the other hand, only the sound intermediate frequency signal is extracted by a sound filter 25, demodulated by a frequency demodulation circuit 27 to a sound signal, then amplified by a sound amplifier 29, and supplied to a speaker 31.
FIG. 2 is a block diagram showing conventional circuit structure of the video detection circuit 17. The VIF signal from the intermediate frequency amplifier 15 is inputted in a bandpass filter 33, which is formed by a surface acoustic wave filter, for example. The bandpass filter 33 has such bandpass characteristics that the amount of passage of the frequency f.sub.p is -6 dB and having linear inclination within a range of the frequency f.sub.p .+-.0.7 MHz, as shown in FIG. 3. It is well known that correct video detection output can be obtained by the bandpass filter 33 having such bandpass characteristics, as described in "Circuit Design of a Television Receiver", literature issued in 1968 by Radio Gijutsusha, pp. 125-127, for example.
The VIF signal filtered by the bandpass filter 33 is taken in an amplifier 1 and amplified. The amplifier 1 is controlled by an automatic gain control (hereinafter referred to as AGC) circuit 2 to regularly maintain its output in an optimum constant amplitude regardless of amplitude variation in the VIF signal.
Output from the amplifier 1 is supplied to a phase locked loop (hereinafter referred to as PLL) circuit 3 and a synchronous detection circuit 4. The PLL circuit 3 is formed by a voltage controlled oscillator (hereinafter referred to as VCO) 6, a phase shifter 7 for making the phase of output S6 from the VCO 6 lead by 90.degree., a phase detection circuit 8 for phase-comparing output S7 of the phase shifter 7 with output S1 of the amplifier 1, and a lowpass filter (hereinafter referred to as LPF) 9 for filtering output S8 of the phase detection circuit 8 and supplying the same to control input of the VCO 6. When the PLL circuit 3 is locked, the output S6 of the VCO 6 is equalized in frequency and phase to the normal video carrier (frequency: f.sub.p) of the VIF signal, and supplied to the synchronous detection circuit 4. The synchronous detection circuit 4 synchronously detects the output S1 of the amplifier 1 on the basis of this signal, to derive video detection output S4.
This video detection output S4 is outputted to the exterior, as well as fed back to the AGC circuit 2 and a locking detection circuit 10 which are provided in the interior. The AGC circuit 2 detects the amplitude of the video detection output S4, to control the amplification factor of the amplifier 1 so that this amplitude is regularly at a constant level. On the other hand, the locking detection circuit 10 detects whether or not the PLL circuit 3 is locked or unlocked on the basis of the video detection ouyput S4, to control the time constant of the LPF 9. That is, it reduces the time constant of the LPF 9 in unlocking to speed up the response, thereby to widen a capture range of the PLL circuit 3. In locking, on the other hand, it increases the time constant of the LPF 9 to slow down the response, thereby to hardly respond to noise, phase distortion originally provided in the VIF signal or the like. Further correct video detection output S4 can be obtained by utilizing output S10 of such locking detection circuit 10.
FIG. 4 is a circuit diagram showing exemplary structure of the phase detection circuit 8 and the LPF 9. As shown in the figure, a signal S1 obtained by amplifying the VIF signal by the amplifier 1 is inputted in bases of npn transistors Q1 and Q2 of the phase detection circuit 8, while a signal S7 obtained by phase-shifting the oscillation output signal S6 of the VCO 6 by 90.degree. through the phase shifter 7 is inputted in bases of npn transistors Q3 to Q6. The collector of the transistor Q1 is commonly connected with emitters of the transistors Q3 and Q4, while the collector of the transistor Q2 is commonly connected with emitters of the transistors Q5 and Q6 respectively. A constant current source I1 is commonly connected between the emitters of the transistors Q1 and Q2 and the ground level. A double balanced type modulator is formed by the aforementioned transistors Q1 to Q6.
The collectors of the transistors Q3 and Q5 are connected to the collector of a common base/collector pnp transistor Q7, as well as to the base of a pnp transistor Q9. The collectors of the transistors Q4 and Q6 are connected to the collector of a common base/collector pnp transistor Q8. The base of a pnp transistor Q10 is connected to the base of the transistor Q8. All of emitters of the aforementioned transistors Q7 to Q10 are connected to a power supply line lV. The collector of the transistor Q9 is connected to the collector of an npn transistor Q11, while the collector of the transistor Q10 is connected to the collector of a common base/collector npn transistor Q12. The bases of the transistors Q11 and Q12 are connected with each other, while respective emitters thereof are grounded.
In the phase detection circuit 8 having the aforementioned structure, the result of multiplication of the signals S1 and S7 obtained by the double balanced type modulator which is formed by the transistors Q1 to Q6 is outputted as current signals from the collectors of the transistors Q9 and Q10. Difference in these current signals forms the phase detection output S4.
On the other hand, the LPF 9 is formed by resistors R1 to R5, npn transistors Q13 and Q14, a capacitor C1 and a constant current source I2. A bias circuit formed by the resistors R1 and R2, the transistor Q13 and the constant current source I2 defines central voltage of a node N1 by supplying bias voltage from the emitter of the transistor Q13. The voltage value of the node N1 is determined around the bias voltage by charging of the capacitor C1 following the phase detection output S8 and discharging of the capacitor C1 through the resistor R3. The voltage value of the node N1 is supplied to the VCO 6 as the output S9 of the LPF 9.
The time constant of the LPF 9 is determined by the resistors R3 and R4, the capacitor C1 and ON state resistance of the transistor Q14 when the transistor Q14 is ON, while being determined by the resistors R3 to R5 and the capacitor C1 when the transistor Q14 is OFF. The base of the transistor Q14 is connected to the collector of an npn transistor Q15. This npn transistor Q15 has a collector which is connected to the power supply line lV through the resistor R6, a grounded emitter and a base which is supplied with the output S10 ("L" in detection of locking and "H" in detection of unlocking) of the locking detection circuit 10.
Thus, the time constant of the LPF 9 is increased when the PLL circuit 3 is locked since the transistor Q15 is turned off and the transistor Q14 is turned on, while the time constant of the LPF 9 is reduced when the PLL circuit 3 is unlocked since the transistor Q15 is turned on and the transistor Q14 is turned off.
The conventional video intermediate frequency signal processing circuit of the aforementioned structure has the following three problems:
(1) When the broadcasting signal is overmodulated (when the deepest modulation factor in the broadcasting signal reaches about 100%, for example), the phase detection output S8 at timing of a deep modulation factor includes a large number of error components and the VCO 6 is inevitably controlled by the phase detection output S8 including such error components. Consequently, the VCO 6 cannot output normal oscillation output signal S6, and hence correct video detection output S4 cannot be obtained from the synchronous detection circuit 4.
(2) Even if the modulation factor of the broadcasting signal is within the range of the generally allowable maximum modulation factor, the phase of the video carrier may be varied with difference in modulation factor in the broadcasting signal due to nonlinearity of the amplification characteristic of a high power amplifier since the broadcasting signal is transmitted from a transmitter through the high power amplifier. When such a broadcasting signal is received by the antenna 11 and taken in the video detection circuit 17 through the tuner 13 and the intermediate frequency amplifier 15, the VCO 6 in the PLL circuit 3 correctly follows phase variation of the video carrier to oscillate. Since the synchronous detection circuit 4 synchronously detects the VIF signal on the basis of the oscillation output signal S6 of the VCO 6, a phasemodulated component is mixed into the sound intermediate frequency signal included in the video detection output S4. This phase-modulated component appears as a sound buzz when the sound intermediate frequency signal is FM-detected.
(3) In the system of simultaneously extracting the video signal and the sound intermediate frequency signal from the video detection output as in the television receiver shown in FIG. 1, the VIF signal is necessarily filtered by the bandpass filter 33 having inclination around the frequency f.sub.p as shown in FIG. 3, for frequency selection. Therefore, the video carrier signal is phase-modulated by an AM component of the VIF signal, as described in Japanese Patent Publication Gazette No. 61-11030 or in the aforementioned literature. The output of the VCO 6 in the PLL circuit 3 correctly follows the same, and a phase-modulated component is mixed into the sound intermediate frequency signal included in the video detection output S4 since the synchronous detection circuit 4 synchronously detects the VIF signal on the basis of the output S6 of the VCO 6. Consequently, a sound buzz is caused when the sound intermediate frequency signal is FM-modulated, similarly to the above item (2).